Receiver latch circuits (sense amplifiers) are extensively used in integrated circuits (ICs) both for inter-chip and off-chip signaling. A transmitter circuit (driver) sends binary data signals through a transmission line (interconnect) to the receiver latch circuit. Since the transmission line may be a lossy channel, data transfer through the transmission line at high rates may result in frequency-dependent attenuation or loss which causes signal distortion in the form of intersymbol interference (ISI). Further, receiver sensitivity is dependent on a common mode (CM) level of the incoming (differential) signal.
The common mode can be overcome by using a direct current (DC) block circuit, i.e., a bypass capacitor. However, a DC block circuit degrades the signal integrity and imposes constraints on the data channel such as keeping high-low density at a certain level by decoding the sent data. Also the capacitor consumes area. Moreover, such solutions do not have true rail-to-rail operation and are not suitable for low voltage signaling. Other solutions such as a complementary input folded cascade amplifier typically consume high power.